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Hi, I'm habing an issue with the systhesis with openlane. With the example works fine. but when I tr...
# openlane
i
Hi, I'm habing an issue with the systhesis with openlane. With the example works fine. but when I try my project I have and error. [ERROR CTS-0056] Error when finding -clk_nets in DB. I tested the design in a FPGA and works, anyone can point me on were I need look in the reports to see why is failing ?
w
Check if the config.tcl has clock defined same as your design
i
yes, I check that, in both the json and the tlc
m
@User the json is ignored if there is a tcl. Can you provide an example? The clock net is used for CTS but the clock port is used for STA
You can look in the early synthesis reports... The exact ones depends on your options
i
set_max_fanout 5.0000 [current_design] [INFO]: Setting RC values... [INFO]: Configuring cts characterization... [INFO]: Performing clock tree synthesis... [INFO]: Looking for the following net(s): main_module.clk [INFO]: Running Clock Tree Synthesis... [ERROR CTS-0056] Error when finding -clk_nets in DB. Error: or_cts.tcl, 57 CTS-0056
this is the full error log
m
Your design would help too. Can you just point to a repo?
i
This is how is implemented in the user example
sure this is the repo
m
It is a little confusing because your instance and module are both "main_module". I'm not sure if that matters...
The repo is using the default clock: set ::env(CLOCK_NET) "mprj.clk"
i
that setting is in the caravel part. Is needed to change that ?
"It is a little confusing because your instance and module are both "main_module". I'm not sure if that matters...". For this in the MPW_2 I have the same name and not issue. I don't know if now affects I will try
m
The clock net in your configuration will be relative to the top of user project wrapper as far as I know
Since you are synthesizing that
Caravel has its own config that you don't need to change since you aren't synthesizing it
i
I'm changing that to test. But I'm doing the hardening of the user_proj_example
I change the net of the wrapper, but same result. I tested one thing, I take the example and remove some of the outputs, and only removing some outputs ( in this case the counter one). And I get a similar error.
so I don't know if is a simplification from yosys and for that the net is not found
Error: or_cts.tcl, 57 CTS-0056. In the error line there is this line. or_cts.tcl is a file in openlane. and the line 57 is this:-sink_clustering_max_diameter $::env(CTS_SINK_CLUSTERING_MAX_DIAMETER)
is not that...
m
Yes, I've run into this before. If you specify an internal net, it may go away if yosys does some buffering of it using its non-clock fanout optization. Can you just specify "clk" in the top level rather than main_module.clk?
i
yes, I try that and same error
I try this. set ::env(CLOCK_PORT) "wb_clk_i" set ::env(CLOCK_NET) "wb_clk_i"
and that manage to work, but I don't know is is correct.
m
cts is called with: -clk_nets $::env(CLOCK_NET)\ so CLOCK_NET must be the name of a valid net. It would be simpler if the clock is in the SDC and that line were just omitted.
m
The one difference is that STA requires a port, not a net...
Slightly different.
i
so is correct that the net and the port is the same? this is correct? or will cause some issues ?
m
They can be the same but they call also be different. For example, if you want to gate the clock in a module with an enable, you should specify the net after the gate but sta will need the net at the input because that is a port. At least, that is my understanding from when I played with it to get my design to work.
i
now I continue the openlane process and I get this error.
[ERROR]: during executing: "openroad -exit /openlane/scripts/openroad/or_resizer_routing_timing.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/routing/15-resizer_timing_optimization.log" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child killed: segmentation violation
so I don't know if is related to the clock net
m
with any case you should file a GH issue with a test case
i
I think, that I found the issue, but not the solution. The problem is in the openlane file "user_proj_example.synthesis.v" the main_module.clk does not appear. When I try the "caravel_user_project" example, the wire conunter.clk appear. So definitely is some kind of optimization that eliminates the net.
m
I'm the counter example, it likely isn't such a high fan-out net so yosys probably doesn't do as much. Can you tell yosys to not touch it?
i
Can you tell yosys to not touch it?, how I do that? I'm new to these synthesis tools.
m
I don't know in yosys
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