Thanks Tom. I'm already using that Matt's doc to run my sta analysis on the hierarchy. But I run this process after all the parts are hardened. What I was curious about was if it was possible for openlane flow to use a previously hardened macro's gl verilog and spefs file, so it can repair setup and hold violations during the placement/routing Although taking a quick look those timing repairs are run in openROAD, and from what I've seen this hierarchical analysis process just runs in openSTA right now

Are you trying to do a hierarchical implementation? You refer to parts as hardended

Sorry I wasn't clear. I have

macro A

hardened by openlane first. Then I want to include that hardened macro in another openlane design, and I would want the flow to use the macro's data (GL verilog and spef?) when hardening that design, so it can detect timing violations and do repairs

You need a timing model extractor to make that work which we don't currently have. That's why my doc is for flat implementation.

out of ignorance for how the internal process works I thought that openlane could do something similar to what your doc does, but in the middle of the flow (with macro's spef files provided by you) so it could use the sta results to make the repairs.