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is there an easy way to pass Verilog `define`s through the openlane flow to yosys for synthesis?

# openlane

aryap

05/13/2022, 9:39 PM

is there an easy way to pass Verilog `define`s through the openlane flow to yosys for synthesis?

Matt Venn

05/14/2022, 6:55 AM

Yes cant remember exactly but search synth in the openlane options

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aryap

05/14/2022, 5:05 PM

thanks matt

Matt Venn

05/14/2022, 5:05 PM

You find it?

Anuj Dubey

05/14/2022, 7:03 PM

Try something like the following. set ::env(SYNTH_DEFINES) "MPRJ_IO_PADS=38" I’ve seen it somewhere but haven't tested it. Let me know if it works.

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aryap

05/14/2022, 8:37 PM

SYNTH_DEFINES

does the trick. thanks

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