Date: Tuesday, August 25, 2020 Time: 16:00 GMT (time zone converter) Mohamed Kassem - The striVe RISC-V SoC Family on SkyWater 130nm Apache 2.0-Licensed Software to Silicon For the first time in the history of the semiconductor industry it is possible to design, verify, manufacture Systems-on-Chip (SoC)'s that have been completely developed using an open source process technology, open source IP and open source design automation environment. In a collaborative effort with Google and SkyWater, efabless' team has designed and implemented the striVe SoC family using SkyWater's SKY130 130nm process, efabless' OpenLANE RTL2GDS no-human-in-the-loop SoC compiler and several key FOSS components including standard cell and IO libraries from SkyWater and OSU, Dual port SRAM created using OpenRAM, PicoRV32 RISC-V CPU and future versions that will include open source eFPGA blocks - all of them are available under the Apache 2.0 license. Mohamed will present the striVe open source SoC family with its 6 configurations which will be publicly released to the design community as concrete designs currently on their way to manufacturing. Being truly FOSS and foundry-enabled, the striVe SoC family will serve as physical demonstrators and be the seed for countless community-defined and striVe SoC's stretching the limits of innovation and to serve select commercial markets.

Has the spec of Strive (configuration tapeout in as a part of shuttle) been publicly available? i am interested in SoC specs, if some one can provides specs like bus architecture, Peripheral supported, Clock speed, PLLs, Timers, Memoires (external or internal) used?