3rd mile-stone in 1-week in field of open-source - 4kB SRAM design
One more time, take a back-seat and appreciate/encourage all freshers like @Yash (who is just in Final year of graduation) to do a similar kind of work, by congratulating them. Again, GitHub is indeed your new Resume
@Yash joined our research project group under VSD Research internship program which runs for 8-weeks. He was supposed to explore openRAM memory compiler flow, develop all custom cells required by openRAM using OSU180nm and generate 4kB SRAM with an access time of 2.5ns
Almost 90% of the tasks have been finished, including pre-layout and post-layout circuit characterization for one corner, as that's what was available openly. There is a last part which needs us to plug all components to openRAM compiler, and we will do it soon.
Here's his GitHub link which shows his masterpiece work of art which includes layouts and characterization results for 6T-cell (read/write operation and stability), N-curve, sense amplifier, write-driver and tri-state buffer
The next part of research will be to port this entire project on google+sky130nm open-process, and make it work with openRAM memory compiler
08/30/2020, 10:16 PM
Interesting. Is there a reason he didn't take the SCMOS cells that come with OpenRAM and scale them?
In looking at the layout, the sense amp and write driver will need to be pitch matched to the bitcell for the no column mux cases.
Let me know if the student wants advice, I'd like to get a 180nm SCMOS going as well.
It would be great to add some SNM utilities as well.
08/31/2020, 1:22 AM
Actually it was a research internship and I had asked them to build all custom cells to build from scratch using OSU180 in 8-weeks, for them to learn. Now this is their full fledged Graduation project.
Yes, definitely want to meet you. Let me DM you to get preferable dates from you. A bit of motivation will really be really encouraging