Hi I think I am getting similar error when I run synthesis f open-source-silicon #general

Channels

mpw-6plus-silicon

pd-openlane-and-sky130

chipignite2206q_stanford_bringup

cadence-virtuoso

fossee-iitb-esim

dynamic-power-estimation

ieee-sscs-dc-23

gfmpw-0-silicon

silicon-validation

fossee-iitb-google-sky130

ieee-sscs-dc-22

mpw-one-silicon

cadence-innovus

verification-fe

foss-asic-tools

openpositarithmetic

openadiabaticlogic

hardware-beginners

design-services

private-shuttle

tapeout-pakistan

rad-lab-silicon

cadence-spectre

mpw-one-clean-short

coalition-for-digital-environmental-sustainability

vlsi_verilog_using_opensource_eda

vlsi_verilog_using_opensoure_eda

openlane_cloudrunner

digital-electronics-learners

verilog-learners

open-microelectronics-textbook

mwcas-2023-rtl2silicon

system-verilog-learners

vlsi-learners-group

chilechipmakers

silicon-validation-private

openhighqualityresonators

waveform-viewers

vendor-synopsys

silicon-photonics

opendataset-circuitnet-for-ml-tasks-in-vlsi-cad

generative-ai-silicon-challenge

community_denmark_dtu

shuttle-precheck

openlane-development

ieee-sscs-dc-21q3

sky130-pv-workshop

verification-be

Title

m

Mili

05/27/2021, 7:59 AM

Hi, I think I am getting similar error when I run synthesis for my design. Can anyone please check if the underlying issue is same?

d

donn

05/27/2021, 10:35 PM

Sorry for the late reply- no, this is a separate issue. It appears that it simply can’t find the module designated as top module.

Please open an issue on GitHub so we can help you further: Thanks https://github.com/The-OpenROAD-Project/OpenLane/issues

m

Mili

05/28/2021, 1:24 PM

@donn Thanks! Will do that.