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Hi Everyone, is anyone able to synthesize systemVerilog using the latest of Yosys?

<https://github.com/The-OpenROAD-Project/OpenLane/blob/f7412929e8775504b9bdc5f247b7f967849a1fc3/scripts/synth_top.tcl#L52-L54>

That needs to be `-sv`  AFAICT. You may want to run a simple check in yosys by itself though, because it only supports a subset of system verilog right now.

The corresponding flag for iverilog is -`g2012` . My experience is that the SV yosys subset is mostly covered by iverilog as well.

Thanks <@U017REC9K36>. <@U01UT7TDH26> and <@U01PEM0B6SZ> can you please try this

I have been running all my sv through <https://github.com/zachjs/sv2v>

Also you can bring all your code into one file at the same time making it easier to move around.

What is Linen?