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m

mehdi

06/10/2021, 9:22 PM
Hi Everyone, is anyone able to synthesize systemVerilog using the latest of Yosys?
That needs to be
-sv
AFAICT. You may want to run a simple check in yosys by itself though, because it only supports a subset of system verilog right now.
The corresponding flag for iverilog is -
g2012
. My experience is that the SV yosys subset is mostly covered by iverilog as well.
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mehdi

06/11/2021, 2:21 AM
Thanks @Steve Kelly. @Ke-Haur Taur and @Peijun Hou can you please try this
a

Andy Attwood

06/11/2021, 8:25 AM
I have been running all my sv through https://github.com/zachjs/sv2v
👍 1
Also you can bring all your code into one file at the same time making it easier to move around.
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mehdi

06/11/2021, 6:29 PM
@Peijun Hou @Ke-Haur Taur