Hey there everyone
Can someone tell me that how do post layout simulations??
I tried pasting testbench file in results/synthesis/ and invoke iverilog there but these modules are missing.
08/21/2021, 10:05 AM
Post layout full simulation can be done in NGSPICE. Also gate level simulation can be done:
Using Icarus Verilog and specifying path to standard cell library declaration.
Keep in mind about a bug: One of instances declare wire 1; which can be safely commented, but it causes simulation to fail