1. What are the typical use cases for utilizing APB over AHB and vice versa?
2. What determines selection of AXI over APB/AHB? Is it just operating frequency or are there some other parameters? At what frequency does we use APB, then AHB and then AXI?
3. Why do we use bridges and not use AXI all over with some modifications like using AXI-Lite where required?
I have gone through their specs but haven't really found satisfactory answers to the above or, I could have missed them. Would really help if someone answers it here!
Thanks, in advance!
02/15/2022, 1:46 AM
Hello @User!!APB as the name suggests is used for peripheral where operating frequency is less. AHB/AXI are central buses. AXI has an advantage of having 5 seperate channels for read/ write which is not the case with AHB.
02/15/2022, 3:54 AM
I am aware of such. Need more specificity.
02/15/2022, 4:18 AM
1. When you dont care about burst speed use APB
2. There is no specefic frequency. You cant make engineering decisions like that. Major contributors are: APB has lowest area. AHB has bigger area and can achieve almost one cycle per data. some minor penalties for initial cycle (1 cycle wasted).
AXI has biggest area, but has the best perfomance and latency. AXI is also the best where you need clock crossing and the best perfomance you got.
Other than that you use what you can. You are not gonna connect axi cpu to ahb bus through converter, then connect another converter from ahb to axi on peripheral sides. Just use tradeoffs to select the parameters you care about then make decision based on that.
3. area, compatibilities. You wont comnect ahb to axi then axi to ahb. Ots waste of resources.
Also there is no need to use full blown axi or axi lite if apb is sufficient. Example: you dont have any clock crossings or need for pipelinening or need for bursts. Use apb then.
02/15/2022, 4:48 AM
Thanks @User for your insights. Could you give some example numbers for area, performance and latency.. ? That will be really helpful !
02/15/2022, 5:19 AM
No, but you can synthesize cores for fpga and see how much resources bus logic takes.
And it's clear that it's that way, since the amount of wires are different. therefore axi > ahb almost always. And ahb > apb since it requires burst logic (counters for burst, more advanced interconnect)
apb can achieve as low as one cycle latency and one data per two cycles.
ahb, same latency penalty as apb, but the bursts means that you can reduce the effect of latency (which is causedd by the peripheral/memory) behind the bursty nature of ahb. Perfomance can go as high as (1+d) cycles for d amount of data
AXI4 can achieve 0 latency, but the main reason to use it, is because axi4 masters can have multiple outstanding requests. This allows to further reduce latency induced perfomance hit.
The performance is d cycle per d amount of data.
In case of ahb/apb, only one request is active on the bus meaning the peripheral/memory latency directly affects perfomance.
axi also uses two "buses" one for read one for write. This allows to even further optimize the hardware, as the one read/write will take an area hit, while not causing any other side effects. For perioherals that can do both read and writes, it improves both perfomance (since bus is not longer shared) and improves latency (since reads are not blocking writes)