Ruediger Ehlers
03/08/2022, 3:39 PM[ERROR]: There are illegal overlaps (e.g., routes over obstructions) in your design.
[ERROR]: See /path/to/project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/27-ext2spice.feedback.txt for more.
at the last steps of the overall hardening flow (for the wrapper)? The said file contains many lines of the following form:
box 80124 41296 80875 41347
feedback add "Illegal overlap between obsm1 and metal1 (types do not connect)" medium
When looking at the generated gds file in klayout, depending on the unit used in that the feedback.txt file, either there is nothing at that place, or the position is inside an SRAM macro.
What would make sense to look for for fixing the problem(s)?Mitch Bailey
03/08/2022, 4:04 PMRuediger Ehlers
03/08/2022, 4:13 PMMitch Bailey
03/08/2022, 4:15 PMArman Avetisyan
03/08/2022, 4:22 PMRuediger Ehlers
03/08/2022, 4:26 PMArman Avetisyan
03/08/2022, 4:39 PMRuediger Ehlers
03/08/2022, 9:08 PMset ::env(PDK) "sky130A"
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_wrapper
#section end
# User Configurations
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) "CONTROL_LOGIC.clk"
set ::env(CLOCK_PERIOD) "10"
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
prj vccd1 vssd1 \
SRAM1 vccd1 vssd1 \
SRAM12 vccd1 vssd1"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project.v \
$script_dir/../../verilog/rtl/monitor.v \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/user_project.lef \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../gds/user_project.gds \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
set ::env(RT_MAX_LAYER) {met4}
# disable pdn check nodes becuase it hangs with multiple power domains.
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
# The following is because there are no std cells in the example wrapper project.
set ::env(SYNTH_TOP_LEVEL) 1
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
# set ::env(MACRO_PLACE_HALO) 4
# set ::env(MACRO_PLACE_CHANNEL) "100 100"
#Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1.
#1 = most reduction, 0 = least reduction
set ::env(GLB_RT_LAYER_ADJUSTMENTS) 0.8,0.8,0.7,0,0,0
# Not too many iterations
set ::env(DRT_OPT_ITERS) 10
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
And as far as the versions are concerned: OpenLane is version 2022.02.23_02.50.41 - OpenPDK commit should be 7519dfb04400f224f140749cda44ee7de6f5e095 (according to the Makefile).Arman Avetisyan
03/09/2022, 5:30 AMMitch Bailey
03/09/2022, 5:56 AMSpecifies explicit power connections of internal macros to the top level power grid. Comma separated list of macro instance names and power domain vdd and ground net names: <instance_name> <vdd_net> <gnd_net>
(Default: macros are connected to the first power domain)
Arman Avetisyan
03/09/2022, 9:31 AMMitch Bailey
03/09/2022, 9:43 AMOptions
menu, unselect Toolbar Hide Locked
. The obsm1
locked layer should be to the right of the unlocked m2contact
.Ruediger Ehlers
03/09/2022, 1:13 PMArman Avetisyan
03/09/2022, 1:15 PMRuediger Ehlers
03/09/2022, 1:18 PM# This makes sure that the core rings are outside the boundaries
# of your block.
set ::env(MAGIC_ZEROIZE_ORIGIN) 0
# Area Configurations. DON'T TOUCH.
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2920 3520"
set ::env(RUN_CVC) 0
# Pin Configurations. DON'T TOUCH
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::unit 2.4
set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
set ::env(FP_IO_VLENGTH) $::unit
set ::env(FP_IO_HLENGTH) $::unit
set ::env(FP_IO_VTHICKNESS_MULT) 4
set ::env(FP_IO_HTHICKNESS_MULT) 4
# Power & Pin Configurations. DON'T TOUCH.
set ::env(FP_PDN_CORE_RING) 1
set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
set ::env(FP_PDN_CORE_RING_VOFFSET) 14
set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
set ::env(FP_PDN_VWIDTH) 3.1
set ::env(FP_PDN_HWIDTH) 3.1
set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
Mitch Bailey
03/09/2022, 1:40 PMRuediger Ehlers
03/09/2022, 1:47 PMbox 80124 41296 80875 41347
for the entry feedback add "Illegal overlap between obsm1 and metal1 (types do not connect)" medium
from /runs/user_project_wrapper/logs/finishing/27-ext2spice.feedback.txt
- I figured that that file contained commands that can be executed by magic.Mitch Bailey
03/09/2022, 2:01 PMRuediger Ehlers
03/10/2022, 9:25 AM