Dear efabless team, Do you have any plans for the near future to add PCIe capabilities to the Caravel so that we can use the chip as a real accelerator (as an example for AI purposes)? @User @User @User

you would probably have to implement the PCIe PHY yourself in the user region, it's kind of outside the scope of caravel for the most part (at least the way caravel is intended currently, it's unlikely to add high speed interfaces directly to the caravel frame)

@User Any ideas of the min area that I need for the phy?

It's hard to say. There dosn't appear to be any existing IP from efabless or previous MPW projects, so maybe check here https://www.synopsys.com/designware-ip/interface-ip/pci-express.html