@User I just give a quick read on the article. I think the MLC is very promising. When we start developing prototypes of RRAM FPGAs at the University of Utah, we see most of challenges coming from (1) limited access to the demanding RRAM technology from foundries; (2) how to stay robust under large process variations and defect rate.

@User our research group have been working on hfox RRAM and we fabricate from our school foundry on back end of the line with 65nm cmos. I have data on both device characteristics stochasticity and yield on wafer. Let me know if you need any info like that. We also have a verilog A model for our devices. That being said I was looking for collab on designing ASIC with our ReRAM devices. If anyone interested, can help.