Hi all, I am trying to generate FPGA fabric using standard cells by following tutorial given in https://openfpga.readthedocs.io/en/master/tutorials/arch_modeling/open_cell_libraries_tutorial/ But iverilog doesn't look for verilog files in the include directory specified in iverilog_output.txt file i.e. iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb -I ${OPENFPGA_PATH }/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2 And generates error as shown in the screenshot attached As a work around I added absolute path in the .v file of the cell included, which worked. Does anyone know why it isn't it searching in included directory for the file defined by -I flag in the iverliog_output.txt file. But even after using the work around, it says simulation successful but for some reason the logs and vcd for the test isn't being generated. It works fine before replacing the cell with the sky130 one, in the xml. Any help would be much appreciated.

@Baloch I did not try too much using iVerilog for Skywater PDK simulation. You may ask @Manar Abdelatty who has done so. As far as I know, they use openPDK instead of the raw PDK.