That is a really cool table. Can't wait to fill it in.

@Teo Ene Thanks. I am curious if you have a metric I can put in the table for the “balance” of an inverter. Do you want the transconductance of the p and n to match? Do you want the inverter to settle at half rail when you short it’s input to output? I am trying to sort out the best inverter to use for analog applications.

I'll have to think more about this question. So far I've just been obtaining and comparing rise/fall delays (not rise/fall times, but rather the delay across the cell). That's the obvious way to measure it. Watching whether the inverter settles at half-rail when gate is shorted to source would be a good solution, but from the spice tests I've been running just now it doesn't seem to exactly correspond to a balance between rise/fall delays. Trying to experiment with these spice simulations is made difficult by the current state of the spice models (only the discrete ones being good)...