Reason, Research and Repeat - RISC-V workshop is back After heavy requests, the cloud-based RISC-V workshop with Steve Hoover is back from the 2nd to the 6th of November, and here's the registration link https://www.vlsisystemdesign.com/riscv-based-myth/ A beginner-level 5-day workshop on “RISC-V based MYTH” (24hrs x 5 days on VSD-IAT platform) When we say, “beginner level”, by end of the workshop you will understand • RISC-V specs • RISC-V software • How to implement RISC-V basic specs using TL-Verilog • Simulate your RISC-V core In short, you are going to write RTL and build the RISC-V core on your own Workshop Day-wise Content : Day 1: Introduction to RISC-V ISA and GNU compiler toolchain 1. Introduction to RISC-V basic keywords 2. Lab Work for RISC-V software toolchain 3. Integer number representation 4. Signed and unsigned arithmetic operations Day 2: Introduction to ABI and basic verification flow 1. Application Binary interface (ABI) 2. Lab work using ABI function calls 3. Basic verification flow using iverilog Day 3: Digital Logic with TL-Verilog and Makerchip 1. Combinational logic in TL-Verilog using Makerchip 2. Sequential and pipelined logic 3. Validity 4. Hierarchy Day 4: Basic RISC-V CPU micro-architecture 1. Microarchitecture and testbench for a simple RISC-V CPU 2. Fetch, decode, and execute logic 3. RISC-V control logic Day 5: Complete Pipelined RISC-V CPU micro-architecture/store 1. Pipelining the CPU 2. Load and store instructions and memory 3. Completing the RISC-V CPU 4. Wrap-up and future opportunities All the best and happy learning