I have performed the lab, but my netlists are not matching, no DRC error in layout

@Junaid Ahmed near the output net you have 2 nfet for ckt 1 while only 1 for ckt 2.

how can I fix it?

Send schematic

screenshot?

Yes screenshot

Capture.PNG

@Junaid Ahmed: The pFET needs to be a 4-terminal device, so you can connect the bulk terminal to power.

@Junaid Ahmed in the circuit 1, 3pins are connected to out net while in circuit2, 2 pins are only connected

okay, thanks I'll try to fix

@Junaid Ahmed: The 3-terminal device might be right; the bulk terminal is specified by a string property. If the string says "vdd" then it would be okay.

name=M2 L=0.18 W=3 body=vdd nf=3 mult=1 ad="'int((nf+1)/2) * W/nf * 0.29'" pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" as="'int((nf+2)/2) * W/nf * 0.29'" ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" nrd="'0.29 / W'" nrs="'0.29 / W'" sa=0 sb=0 sd=0

@Junaid Ahmed: Okay, then I think the schematic is correct and the error is in the layout. nFET seems to be missing the bulk-to-vss connection in the layout, according to the LVS report.

okay

try this @Junaid Ahmed

Thanks above issue is resolved, now the netlist are matched

@Junaid Ahmed: Put the cursor over empty space to the side and type

s

to select the top level view, then do

x

to expand the cell views.