#475 LVS and TLines Issue created by EngGhaith Hi Is there any way to check TLines with LVS? Or they should be shorted in the schematic before Netlist generation? Would masking with IND layer with IND-Ports work? If yes, should we then replace the with inductors in the schematic before creating netlist or what? Thank you in advance. Ghaith. IHP-GmbH/IHP-Open-PDK