#462 SRAM macro models - A_DLY pin Issue created by phsauter The SRAM documentation for the

A_DLY

pin simply states:

Delay setting, adjustment of memory internal timings; recommended setting: Tie to 1

Its function does not seem to be further documented nor is it reflected in either the Verilog or Liberty models. Would it be possible to provide more information on its purpose and if it has externally observable differences (eg interface timings), also add it in the Liberty and/or Verilog models of the SRAMs? If this is not possible or would be too much effort I would recommend an assertion be placed in the SRAM Verilog model that catches it being tied to zero. We just caught this mistake in Croc and while the documentation clearly states it should be tied to 1, it is rather easy to miss at the moment. IHP-GmbH/IHP-Open-PDK