#459 LVS Problem of two in series connected capacitors Issue created by EngGhaith Hi I have two in series connected RFCMIMs and KLayout throws me this error [Image](https://private-user-images.githubusercontent.com/178785944/436198864-d0010078-2e10-4d72-8ed3-6ade2a5b8aad.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NDU4Mjk0NTUsIm5iZiI6MTc0NTgyOTE1NSwicGF0aCI6Ii8xNzg3ODU5NDQvNDM2MTk4ODY0LWQwMDEwMDc4LTJlMTAtNGQ3Mi04ZWQzLTZhZGUyYTViOGFhZC5wbmc_WC1BbXotQWxnb3JpdGhtPUFXUzQtSE1BQy1TSEEyNTYmWC1BbXotQ3JlZGVudGlhbD1BS0lBVkNPRFlMU0E1M1BRSzRaQSUyRjIwMjUwNDI4JTJGdXMtZWFzdC0xJTJGczMlMkZhd3M0X3JlcXVlc3QmWC1BbXotRGF0ZT0yMDI1MDQyOFQwODMyMzVaJlgtQW16LUV4cGlyZXM9MzAwJlgtQW16LVNpZ25hdHVyZT1kZTljMzViNWRmYjBlOTViMWIwYTBkZTBjZTEyYTMwY2EzN2QzYzZhYTU3YmY5ZDQzZDIwODlkNTI1N2Y5MzJiJlgtQW16LVNpZ25lZEhlYWRlcnM9aG9zdCJ9.hPR-z8W4lyQhLq9JIyhTjUTpjhyzxNo-IrXlWsw-G2o) Why? Layout: [Image](https://private-user-images.githubusercontent.com/178785944/436219529-c671f01b-0a08-49f1-82f0-d0b67ec2c223.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NDU4Mjk0NTUsIm5iZiI6MTc0NTgyOTE1NSwicGF0aCI6Ii8xNzg3ODU5NDQvNDM2MjE5NTI5LWM2NzFmMDFiLTBhMDgtNDlmMS04MmYwLWQwYjY3ZWMyYzIyMy5wbmc_WC1BbXotQWxnb3JpdGhtPUFXUzQtSE1BQy1TSEEyNTYmWC1BbXotQ3JlZGVudGlhbD1BS0lBVkNPRFlMU0E1M1BRSzRaQSUyRjIwMjUwNDI4JTJGdXMtZWFzdC0xJTJGczMlMkZhd3M0X3JlcXVlc3QmWC1BbXotRGF0ZT0yMDI1MDQyOFQwODMyMzVaJlgtQW16LUV4cGlyZXM9MzAwJlgtQW16LVNpZ25hdHVyZT1mMzFmMjQ1OWE0ODdjZjQzY2FmYTNlODhmNDQzODY2MTA1NDMzM2FhY2U3N2MxOWJiNmMzNzhkNjdiNTFkZjkzJlgtQW16LVNpZ25lZEhlYWRlcnM9aG9zdCJ9.5S28lJOoETGE6bmwNEkhiTdL1pj5WbM3xKPSwyrcIoI) Schematic: [Image](https://private-user-images.githubusercontent.com/178785944/436219765-b33f0956-7755-445d-b738-9f601434b245.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NDU4Mjk0NTUsIm5iZiI6MTc0NTgyOTE1NSwicGF0aCI6Ii8xNzg3ODU5NDQvNDM2MjE5NzY1LWIzM2YwOTU2LTc3NTUtNDQ1ZC1iNzM4LTlmNjAxNDM0YjI0NS5wbmc_WC1BbXotQWxnb3JpdGhtPUFXUzQtSE1BQy1TSEEyNTYmWC1BbXotQ3JlZGVudGlhbD1BS0lBVkNPRFlMU0E1M1BRSzRaQSUyRjIwMjUwNDI4JTJGdXMtZWFzdC0xJTJGczMlMkZhd3M0X3JlcXVlc3QmWC1BbXotRGF0ZT0yMDI1MDQyOFQwODMyMzVaJlgtQW16LUV4cGlyZXM9MzAwJlgtQW16LVNpZ25hdHVyZT0yZTNmMmNiMzAyYjRlNGVjODM4YWE0M2I3ZjE0NTVjZTA0ODMxZGFlMDQyY2RkOWZkZDU0NGQyZjgxYzI3NTcwJlgtQW16LVNpZ25lZEhlYWRlcnM9aG9zdCJ9.o-BesKfFNcA9f4fbSpWt3KIFbd8ziE0_j0u3cjasrVg) The aim is to connect two caps in series to get the half capacitance, because the min allowd w or l are 7um. BW, Ghaith. IHP-GmbH/IHP-Open-PDK