Here's a simple, functional RISC-V processor and SoC implemented in Verilog and FPGA proven (for learning RISC-V and building cool applications) https://github.com/vsdip/vsdfpga_labs The provided RISC-V core and SoC are *perfect for beginners*—clean, minimal, and easy to grasp. Here’s what makes it special: • Core Features: ◦ Implements 10 essential RISC-V instructions (ALU ops, branches, jumps, load/store, etc.). ◦ Handles all 5 immediate formats (U, I, S, B, J) for instruction decoding. ◦ Simplified 5-stage state machine (fetch, decode, execute, memory, writeback). ◦ Memory-mapped I/O for peripherals (LEDs, UART) and a 6KB RAM. • SoC Integration: ◦ UART communication for serial output. ◦ GPIO control for LEDs. ◦ Clock/reset management and FPGA-friendly design. This code avoids "black box" complexity—every component is transparent, letting you see how instructions execute cycle-by-cycle. Whether you’re simulating the core, modifying the ALU, or adding new instructions, the minimalistic structure ensures clarity. Educators can leverage this to teach digital design, RISC-V architecture, or embedded systems, while students can build real projects like UART-driven apps or LED controllers. P.S. Share this resource with colleagues—turn theoretical knowledge into tangible innovation.