Hello, I have a question about LVS by inductor layout. The PDF Layout Rules talks about inductor verification (6.12 Inductors), but it doesn't talk about substrate connections. Does the inductor substrate implementation follow any rules?

What do you mean by "... the inductor substrate implementation " ? In general the inductor LVS rules does not involve substrate just follow the rules from the LRM.

My question is how to implement the inductor substrate (if it follows, it needs to be close to the inductor, far away, layers, ...). And if I follow the PDF Layout Rules that talk about inductor verification (6.12 Inductors) and add the inductor information to the CDL/SPICE netlist, would it be possible to extract the inductor?

@Krzysztof Herman I think what @JOERDSON TIAGO BATISTA DA SILVA is asking is that there will be a difference in the parasitic capacitance between an inductor over substrate (most often at ground level) and an inductor over nwell. Most likely, you’d need 2 rules to extract the 2 different types of inductors. You could extract them to the same model though.

My question is more basic. I have doubts about how to connect the Bulk Node Connection of the inductor (do I use the Nwell layer? another way? Is there any rule?). And if it is possible to do the LVS verification of the inductor by Klayout (adding the inductor information to the CDL/SPICE netlist and following the inductor rules from section 6.12, of the Layout Rules).