Hello, I was wondering if it is possible to change...
# xschemd
Daniel Herrera
03/27/2025, 6:20 PMHello, I was wondering if it is possible to change the pulse width of a clock signal if I pass it through an inverter while varying VDD?
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Nicklaus Thompson
03/27/2025, 10:14 PMThat's interesting, are you trying to modulate rise and fall time?
Nicklaus Thompson
03/27/2025, 10:14 PMIf so, you can probably just run a transient while sweeping VDD and see what the waveforms look like
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Daniel Herrera
03/28/2025, 2:51 AMYeah I simulated this setup and it seems like the pulse widths aren't changing only the amplitudes. I'm wondering if maybe the pulse width changes are too small to see or that this method might not work.
Daniel Herrera
03/28/2025, 2:56 AMI also wanted to see if it was possible with a current starved inverter setup but I'm not seeing any changes in pulse width either so I'm rather stuck. I'm trying to use a voltage controlled delay element in a PWM circuit eventually.
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Nicklaus Thompson
03/28/2025, 2:58 AMWhat happens if you increase the clock frequency?
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Daniel Herrera
03/28/2025, 3:03 AMIf i increase the clk frequency to 1MHz the same thing happens where the output amplitude decreases and pulse widths don't change
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Nicklaus Thompson
03/28/2025, 3:09 AMHow far up can you go before something interesting happens?
Nicklaus Thompson
03/28/2025, 3:10 AMAlso, try messing with the device widths next
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Stefan Schippers
04/02/2025, 2:02 PMThe clock period is 10 or 100us, this is a very long time, compared to delays you can get with a 1pF capacitor.
Moreover the inverter is delaying the rising and falling edges, so the duty cycle is not changing much.
Also ensure you have assigned the correct supply names (VDD, VSS) to inv_1 inside inv_bulk (click and press 'q' to verify).
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Nicklaus Thompson
04/02/2025, 2:41 PMMaybe the answer to this problem is using switch caps to detect the input level and change the load capacitance accordingly
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Stefan Schippers
04/02/2025, 2:58 PMoutput.mp4
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