Hello everyone, I have a question about how to perform the LVS verification of an inductor. How do I associate the inductor layout with the schematic? So that the LVS is clean.

@JOERDSON TIAGO BATISTA DA SILVA For the sky130 process, I specified the inductor cell as an abstract cell and then had that compared as a device in netgen. In order to prevent the ports from shorting when extracting, I had to add metal resistor.

Interesting. For the IHP process, is it the same thing? Or does it have other forms?

I’m not familiar with the IHP process LVS setup. Klayout would probably require a different approach. You should be able to do the same thing if there’s a magic/netgen LVS flow available.

@JOERDSON TIAGO BATISTA DA SILVA since IHP-Open-PDK is still under development we have not yet integrated a full support for inductor devices. What we have right now is a PyCell for klayout. The LVS in our PDK is based on klayout and it compares CDL/SPICE netlist with the extracted devices. Still there is no inductor available in the LVS deck.