GitHub
03/20/2025, 8:28 PMpSD
layer is only 0.18u around the Activ
of PMOS. But in addition to that there is a required extension of 0.3u around the gate (for LV) and 0.4u (for HV).
I naivly did this which seems to fix my immediate issue but is probably not the right way to go about it. ( It only considers plain old PFETs and none of the other devices types )
( cc @RTimothyEdwards )
diff --git a/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.tech b/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.tech
index b3f272b..cc707bb 100644
--- a/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.tech
+++ b/ihp-sg13g2/libs.tech/magic/ihp-sg13g2.tech
@@ -722,6 +722,8 @@ style gdsii
grow 180
bloat-or allpactivetap * 30 allnactivenontap 0 isodiffres 150
bloat-or allpactivenontap * 180 allnactivetap 0
+ bloat-or pmos * 300
+ bloat-or hvpmos * 400
and-not transhalo
and-not varactorarea
or sealc
IHP-GmbH/IHP-Open-PDK