I'm trying to simulate a non overlapping clock generator and Im not observing any non overlapping clock signals being generated. Does anyone know what the issue could be?

You have 2 inverter delay ... the "non overlap" will be in the order of a few hundreds of ps at best, you're way too zoomed out to see any of that.

I think the problem may be the spice library or the std cells? Because I simulated a single inverter and its not working.

Standard cells need power ...

Add a

VCC

node biased at 1.8V with a voltage source , then edit all gates and set:

VGND=GND VNB=GND VPB=VCC VPWR=VCC

(You can select all gates by clicking with the

Shift

key pressed, then press '`q`' to edit attributes of all gates in a single shot). Add 50fF (to GND) to the

x3, x4, x5, x6

inv_1

outputs, you will get more delay.