I have a question about magic .spice extraction. I was struggling with it for sometime. I used glayout and has DRC =0 layout and I manually put the labels and ports. However, I am not seeing any ports in the extracted .spice file. I have attached my layout in magic and the extracted spice file. * NGSPICE file created from csamplifier_diodeconnectedload.ext - technology: sky130A .subckt transformed_1cd41f5b a_191_n100# a_128_n522# a_53_n100# a_n194_n296# a_n131_n100# + a_n269_n100# VSUBS X0 VSUBS VSUBS VSUBS VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=1.56 ps=11.12 w=1 l=0.3 X1 a_191_n100# a_128_n522# a_53_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=0.39 ps=2.78 w=1 l=0.3 X2 a_n131_n100# a_n194_n296# a_n269_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=0.39 ps=2.78 w=1 l=0.3 X3 VSUBS VSUBS VSUBS VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=0 ps=0 w=1 l=0.3 .ends .subckt csamplifier_diodeconnectedload Xtransformed_1cd41f5b_0 transformed_1cd41f5b_0/a_191_n100# transformed_1cd41f5b_0/a_128_n522# + transformed_1cd41f5b_0/a_53_n100# c_route_2875e6a4_0/m1_n439_n296# c_route_2875e6a4_0/m1_n439_n296# + transformed_1cd41f5b_0/a_191_n100# VSUBS transformed_1cd41f5b .ends I really need help as I am planning to submit my design in April.

@Nimasha silva it looks like magic is not recognizing any text or ports. Can you share your gds input file to magic?

yes. here it is

I don’t see any labels or pin shapes in that gds.

the problem is after I put the labels and ports it does not save when I load again. for extracting, I use these commands after selecting the whole layout. save extract all ext2spice all ext2spice am I missing something? I also attached the gds file which I just updated with 2 ports.

@Nimasha silva Sorry, but I don’t see any text or pins in that gds either. The gds -> magic -> gds flow can cause problems. If you’ve created the gds with glayout, then I suggest that you add the ports and pins in klayout.

Now I used klayout to put the names of ports and then open in magic and extracted the .spice. now I am able to see the names in my netlist. * NGSPICE file created from csamplifier_diodeconnectedload.ext - technology: sky130A .subckt transformed_96b4aecb a_191_n100# a_128_n522# a_53_n100# a_n194_n296# a_n131_n100# + a_n269_n100# VSUBS X0 VSUBS VSUBS VSUBS VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=1.56 ps=11.12 w=1 l=0.3 X1 a_191_n100# a_128_n522# a_53_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=0.39 ps=2.78 w=1 l=0.3 X2 a_n131_n100# a_n194_n296# a_n269_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=0.39 ps=2.78 w=1 l=0.3 X3 VSUBS VSUBS VSUBS VSUBS sky130_fd_pr__nfet_01v8 ad=0.39 pd=2.78 as=0 ps=0 w=1 l=0.3 .ends .subckt csamplifier_diodeconnectedload Xtransformed_96b4aecb_0 vout vin GND VDD VDD vout VSUBS transformed_96b4aecb .ends

@Nimasha silva Great! Thats the first step. Now you need to make sure that the test is recognized as a port. You do this by creating a rectangular shape on the layer/pin layer. Normally people add this directly under the text. Once you’ve added these, you should exttract a netlist that has the following line.

.subckt csamplifier_diodeconnectedload vout vin GND VDD