Does someone have a tutorial on how to do parasitic extraction in xschem. Its urgent thank you

Xschem is a schematic editor, so it is a frontend tool. The schematic then gets drawn using a layout drawing tool (like magic and klayout), following the process design rules and using the appropriate layout mask layers. When the design is complete you can compare layout and schematic (LVS) . When schematic and layout are equivalent you can get from the layout tool the parasitic extraction, that is all parasitic capacitors due to fringing / coupling in addition to the silicon devices (mosfets, resistors, capacitors etc) that are reported with the actual geometries, including parasitic ones (like drain / source areas and perimeters for Mosfets). This returned netlist can be simulated (post-layout simulation) so you can verify if your original design still meets the design specifications.