Hello all - This past weekend I've been studying some the design and build process of CLEAR, and I was just wondering if anyone knows if there was maybe a constraint reason (timing, routing, DRC or otherwise) why there appears to be a lot of extra decoupling capacitance margin around the FPGA core in the taped out user project area? If not at some point I may experiment with trying to adding another row of CLB tiles or maybe something else interesting and see how the routing, timing and mpw_prechecks scripts react.

I don't think there was a particular reason why there's so much unused area. Possible the routing between the fabric and management SoC got congested (but unlikely as there's so much space). Btw. I would like to let you you know about the FABulous project. It's similar to OpenFPGA, but targets nextpnr instead of VPR. See here for more: https://fabulous.readthedocs.io/en/fabulous2.0-development/

Thanks @Leo Moser for the commentary and the link to the FABulous stuff - Do you know maybe if there is some sort of slack/discord/IRC channel where these developers/users hang out? I'd be interested in listening in if allowed.

You're welcome! AFAIK they have an internal communication channel on Skype, but I communicate with them over GitHub Issues and Discussions. Just ask your questions, they are very helpful 🙂