TLDR: Could someone please confirm if the VSDBabySoC integration on the Caravel harness is fully complete and tested? I'm seeing discrepancies in the IO configurations and build issues that might indicate incomplete integration. repo: https://github.com/manili/vsdbabysoc_mpw3 Hey everyone, I've been working with the VSDBabySoC for a few months now and recently attempted to verify it within the Caravel harness. I've noticed a few things that are a bit off: • The README mentions configuring the lower 8 IO pads, but the code configures pads 14-17 as analog. • When following the instructions in the verilog/dv directory, I encountered errors due to missing modules referenced in caravel.v. I ended up manually merging some modules (including mgmt_core_wrapper.v) into single files, even though these files aren’t supposed to be modified by the user. • After these adjustments, running the build in the Docker container resulted in a "Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed" error, and the waveforms indicate that the firmware isn’t being loaded. Could you please clarify whether the integration is considered complete and thoroughly tested? Any insights would be much appreciated. Thanks!