If you are an Indian working in Semiconductors, this should matter to you! We are one step closer to the One Tape-out Per Student vision for India. VSD has just released and made public a RISC-V based SoC designed using SCL 180nm PDK and Synopsys tools. The design is functionally verified and matched with GLS using SCL PDKs. A BIG Thanks to SFAL, Synopsys, efabless and SCL to come together towards "Make In India" initiative. Read blog for more details and stay tuned for progress on this front 🙏 https://www.linkedin.com/posts/kunal-ghosh-vlsisystemdesign-com-28084836_one-tapeout-per-activity-7297656342318628864-zpRK?utm_source=share&utm_medium=member_desktop&rcm=ACoAAAeZe4ABRnXXgcvVesykjXO-9WZxOuR05PE