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<@U016EM8L91B> <@U02UAUGSQ22> <@U01RSNFAM55> we ha...
# ihp-sg13g2
k
@Tim Edwards @Harald Pretl @Boris Murmann we have a question about introducing a separate symbol and pycell of a guard ring and also a global symbol 
sub!
in our PDK. Electrically these guard ring devices are just ptap1 and ntap1 with the respective resistance. The 
w
and 
l
parameters define the guard ring size while 
d
define the ring width. There are two purposes of this device: (1) to annotate on the schematic the use of guard ring and let the layout designer know that a specified bloc should be isolated/shielded by a guard ring; (2) have a dedicated entry in the netlist which will allow auto generation of a guard ring based on the size. Right now the devices are netlisted as follows:
Copy code
XR1 net1 net2 ntap1 R=17.8 w=6e-6 l=6e-6 d=0.31e-6
XR2 net3 sub! ptap1 R=17.8 w=6e-6 l=6e-6 d=0.31e-6
While a regular ptap1/ntap1 devices are annotated without 
d
parameter
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XR1 net1 net2 ntap1 R=268.2 w=0.78e-6 l=0.78e-6 
XR2 net3 sub! ptap1 R=268.2 w=0.78e-6 l=0.78e-6
Actually 
w
, 
l
and 
d
are not used by the simulator which only considers 
R
, however based on these params a layout cell can be generated. So the question is if you consider useful this kind of approach ?
t
I have never seen any other foundry or PDK use this approach. I would normally expect that guard rings and taps would be extracted as parasitic devices, and the parasitic extraction would take care of handling the resistance through the ring and substrate near the device. Otherwise, I have issues with how the tap can be extracted. How is the guard ring automatically detected as a device rather than as part of the layout geometry? Are only complete rings considered? If so, why not any tap? Where are the points of contact in the layout that correspond to the pins in the schematic? Full parasitic extraction will have to know how to exclude any areas that are declared as devices, and the parasitic extraction will be correspondingly less accurate because the entire tap area will be represented as a single resistor between two arbitrary points instead of a resistor network properly capturing the details of the tap geometry.
h
I haven’t fully thought this trough, but I think this could be useful for certain cases, where enhanced isolation is important. I hope one can use the guardring pycell in the layout without having a symbol in the schematic? Like optional symbol, but not required. Or would one have to use ntap1/ptap1 for this purpose?
b
I also have mixed feelings about this. On one hand, I like the idea of auto generating these rings from the schematic. But on the other hand, it could clutter up the schematic too much if required for each ring (echoing Harald's point).
Zooming out a little further, IMHO the whole nomenclature about "guard rings" is misunderstood by a huge fraction of our community. A p+ ring in a p- substrate or an n+ ring in an n-well are substrate or well taps, NOT guard rings. They are just ohmic connections that supply majority carriers.
An actual guard ring supplies minority carriers, e.g. an n+ ring in p- substrate.
h
@Boris Murmann good point on the nomenclature! I think I am guilty of this imprecise usage myself. Will use „taps“ more often 😀
b
With this distinction in place, there does not seem to be a good reason for putting a symbol for well or substrate taps into the schematic. These are not optional, but required. Now, what the exact location and shape is, that is another question, defining that in a schematic seems difficult.
Having a symbol for an actual guard ring that collects minority carriers may be a better idea, although the geometry question is still on the table (I think Tim mentioned this). On the other hand, I like the idea of having true guard rings documented in the schematics.
t
@Boris Murmann: Likewise, I have to plead guilty for using incorrect nomenclature. I will need to get it out of my scripts, as well. . . I do have an opinion on how this should be handled in schematics. A tap ring is like many other things that ought to be part of a device layout, although it may be optional. At least in Magic, I handle various layout-specific options as additional parameters to the device. They are not SPICE model parameters, since they aren't recognized by the model. Maybe there is a way that this is handled in commercial tools, but otherwise I think that we need to define a method by which layout hints are created in a schematic and passed to whatever tool converts from the schematic netlist to layout. Much like synthesis hints are passed in verilog with a 
(* ... *)
comment, layout hints could be passed with a SPICE comment, like 
** LAYOUT-PARAMS param1=value1 param2=value2 ...
. Then the schematic can specify whether the device has a tap ring, or whether ports need to be contacted up to some metal layer, or if there should be a deep nwell under the whole circuit, etc., according to whatever parameters are handled by the device (pycell) generator.
b
@tim I think is pretty much how it's done in many commercial PDKs that I have worked with. The transistor symbol has a bunch of attributes that will be picked up by pcell generation (no extra symbols needed).
While we're on this subject, how do people feel about having a 5-terminal symbol for the PMOS? I'd find that useful. Many people don't understand/know about the extra junction cap from well to substrate and get burned by it.
t
Likewise for NMOS in pwell in deep-nwell. I have used PDKs where there were 5- and 6-terminal MOS devices. The more general practice is to use the same device model whether in or out of deep nwell (which is a bit of a different question than you asked), and I have never understood why that would not make such a difference as to require a completely different device model. I have also seen subcircuit models that include the well-to-substrate diode, which then just produces the problem of knowing whether to extract the diode as a parasitic or assume that it is part of the model.
h
@Boris Murmann re 5-term PMOS: as an additional symbol could be useful, as only option I fear cluttering. If the nwell-sub junction cap is important I am in favor of adding a respective diode symbol. However, that works only for the ones knowing about this. To protect the innocent, only a 5T-PMOS works, as then everybody is looking at an unexpected terminal and is forced to think about it 😀
b
Yes, it would the same MOSFET model, just allows people to show in a schematic that they have thought about the parasitics a bit more deeply in the design phase. Of course, one can always add a diode manually, but as Harald said, it's nice to give people a hint about these extra diodes for in the innocent. We still need the usual 4-terminal device for situations where the 5th terminal just won't matter.
k
Thank you for all the suggestions and the fruitful discussion. I will bring it to our IHP group and surely we will follow the discussion. Definitely we can implement the 
tap ring
as an additional option of our pycell devices, like it is done in Magic. We will have to deal somehow with the ptap1/ntap1 device recognized by LVS. The original idea of having a guard/tap ring symbol was to annotate, which schematic elements should be enclosed by such kind of protection also giving the possibility to simulate it and automatically instantiate on the layout. Maybe it should be a cell property ? Since these elements are usually sized during layout elaboration, a feature of schematic back annotation would be welcome, I guess. As for 6 terminal device we will soon introduce isolated mosfets where additional terminals appear.
t
@Boris Murmann: An actual guard ring supplies minority carriers, e.g. an n+ ring in p- substrate. Quote from Behzad Razavi, Design of Analog CMOS Integrated Circuits, 19.3 "Substrate Coupling": "A guard ring may be simply a continuous ring made of substrate ties that surrounds the circuit, providing a low-impedance path to ground for the charge carriers produced in the substrate." So it seems that the term "guard ring" is used loosely, but also pretty universally. Is there any reference you can point me to that has a thorough discussion of the relative benefits of partial vs. complete rings, majority vs. minority carriers, and single vs. double rings?
b
Yes, it used loosely and I think it's an unnecessary loss of information to call everything a guard ring.
See answer by ericl.
I'll try to find a better reference in a book or paper today.
t
Still, ericl's answer, at the end, describes a guard ring as "p+ on p tied to [ground]" or "n+ on n tied to [power]" which, unless I'm interpreting it wrong, is a substrate or well tie, only one of the opposite type than the bulk of the transistor that it is protecting. Whereas you (I think) are describing a diode surrounding the device but sitting in the same bulk type as the device. I can see that they both serve the same purpose but I don't grasp the relative merits other than the physical area required for the ring.
b
I am struggling to find my definition in a widely read paper or book, but I have personally (and with colleagues) differentiated between rings that address minority carriers versus majority carriers since I entered the industry. The first use of the term guard ring is, as far as I can tell, associated with collecting minority carriers. There are papers from the 60s to 80s that introduce the concept. Here is a nice example:
Epitaxial_layer_enhancement_of_n-well_guard_rings_for_CMOS_circuits.pdf
t
I like these discussions. They make me think hard about things I usually take for granted.
b
The way such a guard ring works is very different from what I call a substrate/well tie and I hence do not call the latter guard rings. Also think about what we call a guard ring in PCB design, it is not an ohmic contact to something.
Alas, today's literature calls everything a guard ring that looks like a ring and is supposed to do something great.
Here's what Gen AI things about it:
Both guard rings and substrate ties are techniques used in integrated circuit design to improve noise immunity and prevent latch-up, but they serve slightly different purposes: Guard Rings: * Purpose: Primarily used to isolate sensitive circuits from noise generated by other circuits on the same chip. They act as a barrier to prevent noise from propagating through the substrate. * Structure: Typically a continuous ring of heavily doped semiconductor material (e.g., p+ for a p-type substrate or n+ for an n-type substrate) surrounding the sensitive circuit. * Mechanism: The guard ring provides a low-impedance path to ground for noise currents, effectively shunting them away from the sensitive circuit. Substrate Ties: * Purpose: Primarily used to provide a stable and low-resistance connection to the substrate. This is important for proper biasing of transistors and preventing latch-up. * Structure: Consists of multiple connections to the substrate, typically spaced evenly across the chip. These connections can be made using heavily doped regions or by connecting to a dedicated substrate contact layer. * Mechanism: Substrate ties ensure that the substrate is at a well-defined potential, preventing voltage fluctuations that can lead to latch-up or other problems. Key Differences: * Primary Function: Guard rings are for noise isolation, while substrate ties are for substrate connection and latch-up prevention. * Structure: Guard rings are continuous rings, while substrate ties are multiple individual connections. * Placement: Guard rings surround sensitive circuits, while substrate ties are distributed across the chip. In summary: * Guard rings are like a fence that keeps noise away from sensitive circuits. * Substrate ties are like anchors that ensure the substrate is stable and well-connected. Often, both guard rings and substrate ties are used together to provide comprehensive noise immunity and latch-up protection in integrated circuits.
Confusing at best, but it suggests that something is a guard ring as soon as it's a ring, as opposed to a local point-like tap.
t
I would not ask an AI to explain something that is "widely misunderstood", because that's what the AI has been trained on. . .
b
These slides from Phil Allen have a nice diagram on the difference between the two rings, see slide 16 in the second PDF below.
lecture08-160425.pdf
t
So what Phil Allen is showing is a substrate tie of an NFET acting as the guard ring (or guard band, maybe) for a neighboring PFET, and the well tie of a PFET acting as the guard band for a neighboring NFET.
b
Yes, I think you are looking at slide 17. To me, none of these are guard rings, just ohmic contacts to manage IR drop.
Actually, the n-well can be thought of as acting as a guard band for the NFET...
It's just more of an accident than something done purposely.
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