Diarmuid Collins
01/28/2025, 10:04 PMDiarmuid Collins
01/29/2025, 10:08 PMStefan Schippers
01/31/2025, 1:43 PMInput_Stage_OA1
• Input_Stage_OA2
• x1_x32_OA
• Universal_R_2R_Block2
• Output_OA
If you can send the missing files I can do some tests on the complete design. As I have it now some errors are real since some nets don't connect anywhere as shown below. in the sub blocksStefan Schippers
01/31/2025, 1:50 PMStefan Schippers
01/31/2025, 1:56 PMStefan Schippers
01/31/2025, 2:09 PMStefan Schippers
01/31/2025, 2:21 PMStefan Schippers
01/31/2025, 2:31 PMStefan Schippers
01/31/2025, 2:40 PMStefan Schippers
01/31/2025, 2:50 PMDiarmuid Collins
02/01/2025, 7:56 AMDiarmuid Collins
02/01/2025, 7:59 AMStefan Schippers
02/01/2025, 11:27 AMvssa,vdda,7*vssa,vdda
expands to:
vssa,vdda,vssa,vssa,vssa,vssa,vssa,vssa,vssa,vdda
. manual page here.
Note: Do not add spaces between commas, as you correctly did in the example above.Stefan Schippers
02/01/2025, 11:31 AMStefan Schippers
02/01/2025, 11:45 AMDiarmuid Collins
02/01/2025, 5:50 PM