Hello @Tim Edwards, together with @Alan Eduardo Rivera Sandoval, @Felipe Rifo, @Daniel Arevalos and @Nelson Salvador we are trying to bring up a chipignite chip from run CI2311. It's a mixed-signal power converter, and we can get some analog signals "do stuff", but the digital modules don't seem to respond. We suspect that the digital pads may not be working properly, so we are double checking the PCB biasing and the OEB settings. Just to know if there are other teams in our situation, do you know if there are already any successful bringups for this run? We may also come back with morespecific questions, I hope this is fine (and that this is the correct channel).

@Jorge Marin I’m rerunning the backend checks. I’ll let you know if I find anything.

@Tim Edwards @Mitch Bailey @Matt Venn many thanks the repo is the following: https://repositories.efabless.com/ac3e_chile_chipathon_team/AC3E_Open3LFCC_V2_repo and our settings for the user_defines.v are pasted below the operation of our converter depends on setting a register designed within a digital block, but whatever we do we don't see any changes in the converter analog outputs... do you have any advice on how to do a "hello world" for the digital section? we suspect there could be some pin setting issues

// SPDX-FileCopyrightText: 2022 Efabless Corporation

//

// Licensed under the Apache License, Version 2.0 (the "License");

// you may not use this file except in compliance with the License.

// You may obtain a copy of the License at

//

//      <http://www.apache.org/licenses/LICENSE-2.0>

//

// Unless required by applicable law or agreed to in writing, software

// distributed under the License is distributed on an "AS IS" BASIS,

// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

// See the License for the specific language governing permissions and

// limitations under the License.

// SPDX-License-Identifier: Apache-2.0

 

`default_nettype none

 

`ifndef __USER_DEFINES_H

// User GPIO initial configuration parameters

`define __USER_DEFINES_H

 

// deliberately erroneous placeholder value; user required to config GPIO's to other

//`define GPIO_MODE_INVALID                  13'hXXXX

`define GPIO_MODE_INVALID                  13'h0000

 

// Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v

// Useful GPIO mode values.  These match the names used in defs.h.

//

`define GPIO_MODE_MGMT_STD_INPUT_NOPULL    13'h0403

`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  13'h0801

`define GPIO_MODE_MGMT_STD_INPUT_PULLUP    13'h0c01

`define GPIO_MODE_MGMT_STD_OUTPUT          13'h1809

`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   13'h1801

`define GPIO_MODE_MGMT_STD_ANALOG          13'h000b

 

`define GPIO_MODE_USER_STD_INPUT_NOPULL    13'h0402

`define GPIO_MODE_USER_STD_INPUT_PULLDOWN  13'h0800

`define GPIO_MODE_USER_STD_INPUT_PULLUP    13'h0c00

`define GPIO_MODE_USER_STD_OUTPUT          13'h1808

`define GPIO_MODE_USER_STD_BIDIRECTIONAL   13'h1800

`define GPIO_MODE_USER_STD_OUT_MONITORED   13'h1802

`define GPIO_MODE_USER_STD_ANALOG          13'h000a

 

// The power-on configuration for GPIO 0 to 4 is fixed and cannot be

// modified (allowing the SPI and debug to always be accessible unless

// overridden by a flash program).

 

// The values below can be any of the standard types defined above,

// or they can be any 13-bit value if the user wants a non-standard

// startup state for the GPIO.  By default, every GPIO from 5 to 37

// is set to power up as an input controlled by the management SoC.

// Users may want to redefine these so that the user project powers

// up in a state that can be used immediately without depending on

// the management SoC to run a startup program to configure the GPIOs.

 

`define USER_CONFIG_GPIO_5_INIT  `GPIO_MODE_USER_STD_INPUT_NOPULL 	// RISCV

`define USER_CONFIG_GPIO_6_INIT  `GPIO_MODE_USER_STD_OUTPUT		 	// RISCV

`define USER_CONFIG_GPIO_7_INIT  `GPIO_MODE_USER_STD_OUTPUT 		// MODULATOR

`define USER_CONFIG_GPIO_8_INIT  `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_9_INIT  `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL 	// CONVERTER 3

`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL 	// MUX

`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL 	// MUX

 

// Configurations of GPIO 14 to 24 are used on caravel but not caravan.

`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL 	// ANALOG

`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL 	// ANALOG

`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL 	// ANALOG

`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL  	// ANALOG

 

`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL	// MODULATOR

@Jorge Marin: I cannot find such a repository. Do you have an upstream repository on github?

@Tim Edwards no, we don't, we worked there directly maybe I can add you as collaborator? we have already someone from efabless

@Jorge Marin Is

vdda1

set at 1.8V? There may be some problems if

vdda1

is 3.3V.

@Mitch Bailey Hello, I'm working with @Jorge Marin in the testing of the chip. First

vdda1

is 3,3V, it was designed as a mux power supply. Why do you think this could be problematic? The intended

io_analog

levels go up to 10V in one of the power stages, we have 3 diferents power stages, 2 of them should work with a maximum of 5V and the other one is for 10V. However, for now, we are testing with a maximum of 3.3V.

Hi @Alan Eduardo Rivera Sandoval

First

vdda1

is 3,3V, it was designed as a mux power supply. Why do you think this could be problematic?

1. Since

io_in[12]

is a 1.8V signal, the

inverter2

pmos (which has a

vdda1

supply) is always on. The nmos gate of the inverter is floating. 2. The devices in

inverter2

and

tgate

are thin-ox devices that may not be able to handle 3.3V.

io_analog[8:7]

is ground, right? I’m going to set

io_analog[9]

to 3.3V.

@Jorge Marin: The definitions you have in your

user_defines.v

are old and incorrect, but with a quick glance over it, it looks like the only thing that is wrong is that the "pulldown" and "pullup" definitions are swapped. Since you don't appear to be using either pull-up or pull-down input modes, then you shouldn't be affected.

@Tim Edwards We are testing with the Caravel_Board Rev 5a as a preliminary test to check if the chip is "alive." The tests are being conducted using this board's pins. We have a digital module that works as a PWM-PS modulator and a converter selector. Due to the limited number of pins, this was the chosen approach. In the tests, I'm trying to send signals to this digital module using an FPGA, configuring it to observe some signals on the outputs. However, nothing happened in any of the possible configurations; it seemed as if the signals were not reaching the digital module. In the last tests, I was able to upload new code to the chip:

#include <defs.h>
#include <stub.h>


// --------------------------------------------------------
// Firmware routines
// --------------------------------------------------------

void configure_io()
{

//  ======= Useful GPIO mode values =============

//      GPIO_MODE_MGMT_STD_INPUT_NOPULL
//      GPIO_MODE_MGMT_STD_INPUT_PULLDOWN
//      GPIO_MODE_MGMT_STD_INPUT_PULLUP
//      GPIO_MODE_MGMT_STD_OUTPUT
//      GPIO_MODE_MGMT_STD_BIDIRECTIONAL
//      GPIO_MODE_MGMT_STD_ANALOG

//      GPIO_MODE_USER_STD_INPUT_NOPULL
//      GPIO_MODE_USER_STD_INPUT_PULLDOWN
//      GPIO_MODE_USER_STD_INPUT_PULLUP
//      GPIO_MODE_USER_STD_OUTPUT
//      GPIO_MODE_USER_STD_BIDIRECTIONAL
//      GPIO_MODE_USER_STD_ANALOG


//  ======= set each IO to the desired configuration =============

    //  GPIO 0 is turned off to prevent toggling the debug pin; For debug, make this an output and
    //  drive it externally to ground.

    reg_mprj_io_0 = GPIO_MODE_MGMT_STD_ANALOG;

    // Changing configuration for IO[1-4] will interfere with programming flash. if you change them,
    // You may need to hold reset while powering up the board and initiating flash to keep the process
    // configuring these IO from their default values.

    reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
    reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
    reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
    reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;

    // -------------------------------------------

    reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;     // UART Rx
    reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;           // UART Tx
    reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
    reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
    reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
    reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
    reg_mprj_io_14 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_15 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_16 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_17 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_18 = GPIO_MODE_USER_STD_ANALOG;

    reg_mprj_io_19 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_20 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_21 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_22 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_23 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_24 = GPIO_MODE_USER_STD_ANALOG;
    reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_NOPULL;
    reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_NOPULL;

    // Initiate the serial transfer to configure IO
    reg_mprj_xfer = 1;
    while (reg_mprj_xfer == 1);
}

void delay(const int d)
{

    /* Configure timer for a single-shot countdown */
	reg_timer0_config = 0;
	reg_timer0_data = d;
    reg_timer0_config = 1;

    // Loop, waiting for value to reach zero
   reg_timer0_update = 1;  // latch current value
   while (reg_timer0_value > 0) {
           reg_timer0_update = 1;
   }

}

void main()
{
	int i, j, k;

    reg_gpio_mode1 = 1;
    reg_gpio_mode0 = 0;
    reg_gpio_ien = 1;
    reg_gpio_oe = 1;

    configure_io();

    reg_uart_enable = 1;

    // Configure All LA probes as inputs to the cpu
	// reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
	// reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
	// reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
	// reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]

	// write data to la output
    //	reg_la0_data = 0x00;
    //	reg_la1_data = 0x00;
    //	reg_la2_data = 0x00;
    //	reg_la3_data = 0x00;

    // read data from la input
    //	data0 = reg_la0_data;
    //	data1 = reg_la1_data;
    //	data2 = reg_la2_data;
    //	data3 = reg_la3_data;

    print("Hello World !!\n");

	// while (1) {



//         reg_gpio_out = 0;  // ON
//         reg_mprj_datah = 0x0000003f;
//         reg_mprj_datal = 0xffffffff;

// 		delay(800000);
// //		delay(8000000);

    // }


}

The difference from the original

blink.c

is that I kept the LED turned on and commented out the LA probes section. This new code produced some results, and now the digital module switches RANDOMLY between four different states when performing the same test and reseting the settings register before starting the test. Do you see any issues with the new code?

@Jorge Marin Here’s a screen shot of the

user_defines.v

you shared (left) vs the

user_defines.v

in the default 2311

caravel_user_project/verilog/rtl

(right). Here’s the current link which is the same as was used in the 2311 shuttle.

@Mitch Bailey , @Jorge Marin: If I look through the git logs of the caravel_board repository, references to "REV5A" show up around two year ago. I suggest getting the 5A schematic by cloning the

caravel_board

repository and rolling it back by checking out an appropriate commit like

commit aa2f08084a4f8a04a02ee86e2a9184939731521b

from April 3, 2023, which seems to be the last flurry of commits before work on the Rev 6 board was added. @Passant can acknowledge if that's a good commit to grab the 5A board schematic from.

@Jorge Marin @Tim Edwards @Mitch Bailey: I agree with Tim's suggestion for cloning the repo and rolling back to get the 5A schematic. I suggest checking out to

commit 28d947ebe9b01bbd653606f458ace25de0bbdd63

as it matches the current directory structure or you could download the schematic pdf here also other required files from here