You can make sure that the pin order of the layout matches the schematic by reading the schematic netlist into the layout using the command (in magic)

readspice <netlist>

(you can also manually order the index of each pin, although

readspice

is much more convenient). Once you have two .subckt netlists that have matching ports, you can substitute either one for simulation. If you want the substitution to be automatic, you can change the symbol (by editing the .sym file of the OTA) to set `type=primitive`; that will keep xschem from generating the .subckt for the OTA. Then you can add to the testbench a

code

block that includes the netlist using

.include <filename>

.