#208 [bug] LRM specify block delay path restrictions Issue created by likeamahoney Hi, All! I noticed that in verilog cell file there are a lot of

specify

constraints which are buggy due to LRM:

30.4.1 Module path restrictions

Module paths have the following restrictions:

—The module path source shall be a net that is connected to a module input port or inout port.

—The module path destination shall be a net or variable that is connected to a module output port or

inout port.

Path can't start at output port due to LRM 2017 and it's earliest versions. So Does it correct to specify such constraints in that manner or it's bug in provided cells? I use the `slang` tool for elaboration of designs from https://github.com/IHP-GmbH/IHP-Open-PDK/tree/main . With its help I discovered this IHP-GmbH/IHP-Open-PDK