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Also, this OTA will be used in some bigger circuit comprising of capacitors, comparators and inverte...
# magic
s
Also, this OTA will be used in some bigger circuit comprising of capacitors, comparators and inverters. Should we do the postlayout simulation of each component separately (by building the layout of different components in a different magic file) and then combine them in the final layout of the circuit ? If so, how can we combine the layout of different components in the final layout ? Your answer would be very helpful for me as a beginner in IC design. Thanks in advance.
l
You should simulate the entire system and its main blocks separately before you even make your layout. If you want to make a gm-c filter, you should run sims to measure its transconductance, output resistance, input and output range, etc. You should also run PVT and monte carlo sims.
In your example, it seems you're using single transistors with minimum transistor length. You will have a huge problem with mismatch and flicker noise later on, as the transistors are just too small. The 5T OTA has terrible output range and linearity. You should try a better topology with source degeneration and based on the symmetrical OTA at least.
t
@Shavika Rastogi: Your next step is to make sure that you have labeled your layout with port pins so that you can extract a netlist with the same pin names. Then, you will want to do a basic extraction for LVS in magic using 
extract all ; ext2spice lvs ; ext2spice
. Do the schematic capture from xschem using the menu option 
Simulation->LVS->Top level is a .subckt
. Once you have two netlists, you can compare them using netgen.
s
@Tim Edwards Once we get the successful lvs check done using netgen, how can we proceed with the postlayout simulation ? How to compare the results prelayout and postlayout simulation using testbench ?
t
For post-layout simulation, you want to take your final design and do a full RCX extraction (the set of commands to do this has been posted multiple times and should be found in #C016HUV935L; plus, the script also exists in IIC-Multitools). If you do your testbenches with the circuit-under-test being instantiated as a symbol in the netlist, then you can just replace the original .subckt with the one produced from full RCX extraction. If you set up your testbenches in CACE (https://github.com/efabless/cace), then the RCX extraction is done automatically and you can do direct comparisons of pre- and post- layout simulation.
s
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@Tim Edwards I used the above script for doing the parasitic extraction from my OTA layout
This script generated the following file with parasitic capacitances :
pl_ota.spice
I also generated the netlist from my OTA schematic (gm_mos_bias) which looks like this :
gm_mos_bias.spice
On comparing these two netlists, I found that the sequence of pins (VP, VN, BIAS, MINUS, OUT) mentioned in .subckt definition for these two netlists is different. This might generate different outputs for pre-layout and post-layout simulations. How can we make sure that the sequence of pins in these two .subckt definitions remains same ? How to make sure that pins representing power ports (VP and VN) should always come first ?
Also, I have written the following testbench where I am testing the functionality of OTA as a buffer :
ota_testbench.spice
It can be seen that it contains the .subckt definition of OTA schematic (gm_mos_bias). This is the schematic diagram of OTA as a buffer:
How can I use the same testbench for testing the OTA layout ? Is there a way to visualise the testbench output generated by OTA schematic as well as OTA layout simultaneously (side by side) ?
t
All the ports in magic can be assigned a number and they will come out in that order when doing extraction. See documentation for 
port index
s
@tnt Please send me the link for the port index documentation, if it exists.
m
@Shavika Rastogi you can also use 
readspice
http://opencircuitdesign.com/magic/commandref/readspice.html You can create a testbench schematic that only includes a symbol with type=primitive property. You can include one of two spice files - the schematic version or the post layout with parasitics version.
s
@Mitch Bailey @Tim Edwards I used the "readspice" command in my layout before doing the parasitic extraction this time. I used it like this in my layout window: readspice gm_mos_bias.spice. Before doing that, I made sure that the subcircuit name in schematic and layout is same (in my case it is OTA). After using readspice, it shows : "Annotating port orders from gm_mos_bias.spice. Annotating cell OTA. Cell OTA port order was modified." After that, I did the parasitic extraction using the commands I shared in this chat : extract all ext2spice hierarchy on ext2spice scale off ext2spice cthresh 0 ext2spice -d -o pl_ota_3.spice -f ngspice
This is the file that was generated after doing parasitic extraction :
pl_ota_3.spice
It can be seen that the port order is still different from what was mentioned in the spice file generated from the schematic "gm_mos_bias.spice". This leads to difference in the results of pre-layout and postlayout simulations.
I think that this issue could be because magic is not able to identify power nodes (VP and VN) as global variables. That's why it is not able to distinguish between power nodes and other nodes. How can we make sure that power nodes are always identified as global nodes ? I heard in some of the tools like Cadence, there is a way to define global nodes as VP! and VN!. But I don't know how to define these in magic. Does anyone have an idea how can it be done in magic ?
m
@Shavika Rastogi Can you share 
gm_mos_bias.spice
?
s
@Mitch Bailey Here is the file "gm_mos_bias.spice" that I used with readspice command in magic for deciding the port order:
gm_mos_bias.spice
m
@Shavika Rastogi thanks. @tim any ideas why the port order isn’t picked up?
t
@Mitch Bailey: I don't know, but the fact that the output has 
l=300000u
means that the version of magic is somewhat old. . . I modified the handling of the output a while ago (more than a year, I think) to generate the more standard output of 
l=0.3
. I don't know what other updates and corrections might have been made since that version.
m
@Shavika Rastogi What magic version are you using? 
magic -dnull -noc --version
s
@Mitch Bailey @tim The magic version is 8.3.334
m
@Shavika Rastogi I’m currently using 
8.3.497
. Can you update magic and try again?
s
@Mitch Bailey I am using Skywater PDK and magic inside the docker container provided in this github repo: https://github.com/efabless/foss-asic-tools . Magic is pre-installed in this docker container. Does anyone know how can we update the magic version when we are inside the docker container ?
m
@Shavika Rastogi https://github.com/efabless/foss-asic-tools hasn’t been updated in 2 years. @Kareem Farid do you have any advice? I can probably guess how to change the recipe, but not how to update the efabless docker image. @Anton Maurovic (efabless support) is there a more recent docker image that is recommended?
r
https://github.com/iic-jku/IIC-OSIC-TOOLS is a more up-to-date fork of the foss-asic-tools
s
@Roel Jordans Which version of magic is used in this docker image ?
r
8.3.505
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