The transistor in the north is M2. I would like to tie the bulk of this M2 transistor to source . Could someone help how to define the route such that bulk to source is connected ? I have tried routings such as

straight_route(pdk, top_level.ports["M2_source_E"], top_level.ports["M2_tie_E_top_met_E"], glayer2="met3")

but I can't see the via and the track route getting created from the well ties. Also what is the difference between the definitions of the well ties as in

M2_well_E, M2_tie_E_bottom_lay_E, M2_tie_E_top_met_E

?

Can u try with Met1

A little trick you can use to see all the ports overlayed on the layout is by printing every single port in the layout, then writing the component to gds for key,val in Mytopcomponent.ports.items(): Mytopcomponent.add_label(key,val.center,val.layer)

Thanks @Ali Hammoud for the suggestion, I tried the same . But it wasn't able to overlay the ports in the layout . The reason was all the layers seem returned by

val.layer

seemed unavailable and it returned an error although the text from the key described the port text.

(67, 20), (68, 20), (66, 20), (69, 20), (65, 20), (66, 44), (67, 44), (64, 44), (93, 44)

Are u sure that u added the reference to the top_level?