https://open-source-silicon.dev
Join Slack
1. the LVS seems not to recognize RPPD with bends. and even when it does recognize the npnMPA it thi...
# ihp-sg13g2
o
1. the LVS seems not to recognize RPPD with bends. and even when it does recognize the npnMPA it thinks there are different in schematics and layout with the same default parameter l=2 w=1. is this expected? 2. the PCELL code for the npn13G2 seems not to work in the dev and main branch. so i use the nx=1 variant from ihp-sg13g2/libs.ref/sg13g2_pr/gds/sg13g2_pr.gds. 3. the npn13G2 has no metal at the substrate. but i thing i should connect it to VSS. is this correct? and what is the reason that he cell dont has contacts already? if i should make contacts my self, is it ok to do it only on one side? 4. is there an example how to connect it?
k
@olisnr thank you for reporting. We will review the code of the PyCell to generate the HBT device. Seems that it does not instantiate the core device automatically. I have consulted about this 
pSD + active
outer ring area and it is a kind of floating guard ring. If you connect it to 
VSS
a parasitic capacitance will be created and it will affect the high frequency performance of the device. It is recommended to use 
ptap1
devices in order to make substrate connections.
o
also then i can let it open? or do i need the ptap1? and what should i do in schematics?
can You show me a layout of a test-circuit with the npn13G2?
k
I d not have any layout I could share but a recommendation is to use 
ptap1
devices (which have own model) in order to connect HBT bulk to a 
VSS
o
is the ptap1 connection included in the transistor-model or is it correct, to connect the S of the BJT over a ptap1 to VSS in the schematics?
k
it is not included, the designer is in charge to connect it according to the needs
Copy code
Bipolar Junction Transistors (BJTs)

General form:
    QXXXXXXX NC NB NE <NS> MNAME <AREA> <OFF> <IC=VBE, VCE> <TEMP=T>

Examples:
    Q23 10 24 13 QMOD IC=0.6, 5.0
    Q50A 11 26 4 20 MOD1

NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS is the (optional) substrate node. If unspecified, ground is used.
o
is it ok to connect the S to the E in a differential stage? like i would connect the Bulk to the Source of a MOSFET?
k
only if four emmiter connects to the substrate
o
i dont understand: there are two substrates: the inside and outside substrate of the transistor. is it ok when the emitter is connected to the transistors isolated substrate, and the emitter has a higher voltage then the transistor encircling outside-substrate? needs the inside-substrate be connected to the outside-substrate in any case?
k
that is the recommendation, the designer handles the substrate contact via this port.
o
ok
7 Views
Open in Slack
PreviousNext
Powered by

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.

Powered by