#188 PCells in KLayout Issue created by olisnr i try to use nmosHV, pmosHV and cmim in KLayout from the last working SG13_dev version. my BiG question is: 1. the MiM-capacitor should only use layer 5 and some MiM-layers if i look at 1.1 Main Processing Sequence and Cross-Section Schematic of SG13G2 Process Specification Rev. 1.2. but in KLayout i see also

TopMetal1.drawing

. is this an error ? in DRC i get some errors: 2. pmosHV gives minimum errors DRC for pSD.i1 min 400nm, actual 340nm. 3. pmosHV has no GatPloy.pin but nmosHV has. is GatPloy.pin needed for production? 4. if i use an w=2u l=1u pmosHV i get also NW.d1 and LU.a errors will this be fixed, or is the idea to draw pSD and ThickGateOxyde in the end from hand, when the FETs are placed? IHP-GmbH/IHP-Open-PDK