the graph I'm getting says that the circuit can get >10dB gain at 1THz which seems very wrong

1. Label your nets. 2. Bias your circuit with currents, not voltages. Or, at least, make the input voltages greater than the input. Try 0.5 V at the tail current source transistor instead of 0.8 V. 3. Try AC = 1 at the non-inverting input. From the inverting input to the output, there is no intermediate nodes. 4. Maybe the models aren't calculating the gate-drain capacitances. Are there any values for drain terminal area?

seems odd, I get more sane results when I usea current source in place of the tail current source transistor

@Rita I suggest to use the 4 terminal mos transistor and explicitly set the body terminal to GND (for nfet) and VCC (for pfet). The 3 terminal symbols set the body terminal via attribute (body=VCC or body=GND) and since you didn't put a label on the VCC net i think these are not connected correctly. This will not solve your issue, however is good practice. and as @Luis Henrique Rodovalho said always label your nets , even the ones you think are not interesting, problems always happen on non interesting nets by murphy rule.

even with 4 terminal devices it still gives me the same result

Yes i said that, the problem is not due to the body connections. Please note: M1 and M5 body terminals must be connected to GND not to the current source, unless you draw these 2 transistors into an insulated p-well, which is very unlikely. I also tried this ac simulation and i got the strange positive gain at THz frequencies, I believe the simulation result is not valid at these frequencies and i am investigating.

I've seen the same behavior in my own design FWIW. Have you tried laying out the circuit, extracting, and simulating on the extracted circuit?

I'm getting similar results also... I need to put a capacitive load, otherwise there will be voltage gain at the higher frequencies

Usually I include in open loop simulations the loading of the feedback path. without this loading effect there is >1 gain at unrealistically high frequencies.

Hi Rita, check to see if your hand analysis generally agrees with the spice simulation. Since you are measuring the AC response of transistor M1 to the output node you have a 1 pole system that roles off at -20db/decade. The pole frequency is 1/ (2pi*RC) where the R is the output impedance of NCH input transistor ( labeled M1 on your schematic ) in parallel with the output impedance of the PCH transistor (labeled M3 on your schematic ). The output impedance of a transistor is 1/gds where gds is the small-signal drain-to-source conductance. So the output impedance is: (1/gds_m1) // (1/gds_m3). The output capacitance is [Cds of M1] plus [Cdb of M1] plus plus [Cdg of M1] plus [Cds of M3] plus [Cdb of M3] plus [Cdg of M3]. I am not yet familiar with ngspice so I don't know what small signal parameters ngspice reports. For HSPICE, which I am very familiar with, it will report the small signal parameters of all transistors when you do a dc operating point analysis. (.op analysis)

so I have a working op amp now, but I'm still getting issues with simulation

1. Use multipliers. Forget about using wider transistors. Transistors with different lengths and widths have slightly different characteristics, like threshold voltage. For example, M53,58 should be 1x5/0.5. M56,59 should be 2x5/0.5. M62,63 = 10x5/0.5. M57=10x5/0.5. 2. Use 4 terminal devices. 3 terminal devices have a hidden terminal connected to a hierarchical node. In this case, I think that the PMOS bulk terminals are connected to vdd!. Is there a vdd! connected voltage source? NMOS bulk terminals must be connected to GND and you placed it there, so it must be ok. 3. You are using PMOS cascode devices. For 1.8 V VCC, I'm pretty sure you won't have input or output voltage excursion. Stay away from cascode devices for a while. It doesn't even matter, if the NMOS side of the output stage isn't also in cascode configuration.

it turned out that I just had to change VCC -> VDD