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Can't see anything immediately wrong. Check the trace. Check reset, clock, flash, and power is good. Compare to the examples. I would expect at least 600ms to finish io config

@Edrisborne: If you are reading from the logic analyzer, then you need to set

la_iena

bits to 1 for the channel(s) you want to read back. The purpose of the

la_iena

signals is to allow the user project to leave the logic analyzer unconnected without having to worry about floating inputs. But that means that all data passing from user project to management SoC has to be gated by enable signals that are controlled through the software.

Much appreciated for both your comments. I'll make the changes and see the results.

https://github.com/mattvenn/wrapped_instrumented_adder/blob/main/instrumented_adder_test/instrumented_adder.c]

https://github.com/EdrisTime/caravel_chip thanks

yes I think so, an overview vid

thanks