Anyone know why, or how to update to MPW7 libraries for doing simulations of standard cells?

If you are directly using standard cell in RTL, then you need to include it's verilog module during simulation. This is need for simulator to understand the functional behaviour of the standard cells. You can need add relavent standard cell in your rtl file list. -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v

no, it's analog simulation of the extracted netlist from a standard cell

not sure on the analog simulation.