Does anyone know which version of verilog/systemverilog is supported by openlane?

Whatever yosys supports. So Verilog is pretty much fully supported. Some SystemVerilog are supported to. Best way to know is to try to synthesize your code as you write it. ... or you can use chisel3 that generates pure verilog ... or use surelog or sv2v to convert SystemVerilog to verilog. ... or use commercial flow to generate the netlist (complex and hard)