image.png
r
image.png
s
this is not a flip flop, this is a latch, if B is low input is propagated to output. If B is high output is latched. Connecting Q_N to D will make it oscillate if B is low. Use dfrbp_1
r
what does gate_n do
s
i fgate_n == 0 input D is propagated to Q. If gate_n == 1 output Q keeps last sampled value.
r
image.png
it seems like with this logic gate, the output is low even with D_N = 0
never mind, forgot to set voltage rails