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# general
r
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s
please post the test.xspice file. My guess is that is not a LIB file so it should probably included with a .include directive. But i can not say without looking at it.
r
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I get this from changing .lib to .iclude
*.include
s
@Rita i was also trying to convet a digital netlist to xspice. What are the steps you did? I tried this But can't understand the pin order error. test netlist attached. --FIXED--
Copy code
schippes@mazinga:~$ python3.10 <http://spi2xspice.py.in|spi2xspice.py.in> share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib ~/.xschem/simulations/test_stdcells.spice ./test_stdcells.xspice
Reading liberty netlist share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
Reading spice netlist /home/schippes/.xschem/simulations/test_stdcells.spice
Writing xspice netlist ./test_stdcells.xspice
Writing xspice file
Cell sky130_fd_sc_hd__nand2_1 does not have SPICE pin order defined!
Cell sky130_fd_sc_hd__dfrtp_1 does not have SPICE pin order defined!
Cell sky130_fd_sc_hd__nor2b_1 does not have SPICE pin order defined!
Cell sky130_fd_sc_hd__dlrbn_1 does not have SPICE pin order defined!
Cell sky130_fd_sc_hd__nor2b_1 does not have SPICE pin order defined!
Cell sky130_fd_sc_hd__nand2_1 does not have SPICE pin order defined!
Cell sky130_fd_sc_hd__a31o_2 does not have SPICE pin order defined!
Cell sky130_fd_sc_hd__inv_2 does not have SPICE pin order defined!
Done.
test_stdcells.spice
r
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I ran this script
here's the d flip flop I'm trying to use
I'm unsure where the power pins are but I was told that they were 1.8V
s
@Rita i got my above error fixed by including the standard cell spice file in the netlist before any other line . so i will liik at my xspice file and see if i can move further)
r
?
I am unsure how to fix this
still
s
@Rita are you using sky130 ?
r
yup
I added .include after the .lib line in TT_MODELS
s
@Rita i don't see any DFFIQ in sky130
r
hmm
it's from gates.sch
if you could tell me which D flip flop I should use instead that would be great
s
@Rita your above scripts is non sense, you are trying to give to spi2xspice.py an xschem sym file. See the example schematic 
sky130_tests/test_stdcells.sch
for an example schematic with some stdcells, including a flop. You must create a netlist from it and give that netlist to spi2xspice.py, together with the liberty file of all sky130 gates ($PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib). Try the attached netllist (from above exampel schematic) and run with: 
python <http://spi2xspice.py.in|spi2xspice.py.in> ~/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib test_stdcells.spice ./test_stdcells.xspice
Of course set liberty path to your system installation.
test_stdcells.spice
🌍 1
r
how do I get the .spice file?
I can't find test_stdcells.spice
even after generating netlist and simulating
nvm found it
so what I'll need to do is to do the digital circuits in another file, and then get the .spice file and add it to the simulation with my analog circuits right
s
I guess so, but i am also struggling with it.
@Rita after getting a xspice netlist of a digital subckt i had to tweak the rise_delay/fall_delay/input_load as these numbers were too big. Even after setting reasonable values i don't get any activity from this subcircuit. when simulated with ngspice. I get no warnings or errors so it is accepted however outputs are fixed at 0
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