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Hello All! This is perhaps an uninformed question (I’m more of an analog designer than a digital on...
# openlane
m
Hello All! This is perhaps an uninformed question (I’m more of an analog designer than a digital one), but is it possible to take a netlist generated from xschem using only standard cells and let OpenRoad/OpenLane place and route it? That is, skip the synthesis step? I’ve seen a lot of wonderful documentation on the going from RTL to GDS, but I couldn’t find much on going from a netlist to GDS. If it is possible, would someone be so kind as to direct me to some docs on how to get started? Thanks in advance!!
v
m
@Vijayan Krishnan Ah! That’s awesome! Thank you!
Hello @Vijayan Krishnan I finally got around to trying this and I think I am missing something. I have attached the config.tcl file I’m using and the toy verilog file. One thing that I changed is that the SYNTH_TOP_LEVEL is now deprecated; so I used SYNTH_ELABORATE_ONLY instead. But I get the following error. I think I am exporting the verilog perhaps incorrect?
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[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/elaborate.tcl -l /openlane/designs/dmux2_tcl/runs/RUN_2022.10.09_17.20.36/logs/synthesis/1-synthesis.log |& tee /dev/null"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /openlane/designs/dmux2_tcl/src/demux2.v
/openlane/designs/dmux2_tcl/src/demux2.v:21: ERROR: Parameter x1.VGND with non-constant value!
child process exited abnormally
Do you have any thoughts? Thank you so much!
config.tcldemux2.v
v
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Error-[NCE] Non-constant expression
 The following expression should be a constant.
 Expression: VSS
 "denux2.v", 15
 Source info: .VGND ( VSS ) ,
In parameter list you've defined ports, it is wrong. Parameter list should contain constant values/parameters.
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#(
.VGND ( VSS ) ,
.VNB ( VSS ) ,
.VPB ( VDD ) ,
.VPWR ( VDD ) ,
.prefix ( sky130_fd_sc_hd__ )
m
Hello @Vijayan Krishnan, Thanks for your reply! So I'm exporting this netlist from Xschem....what setting do I need to change?
Or do you have an example project where you did this workflow fully? Thank you very much for your help!!
v
I'm not worked on Xschem. Yosys not able to synthesis this.
m
@Vijayan Krishnan ok. I really don't need any synthesis since I've already chosen parts (and hand calculated timing). Is there a way I can pass a structural verilog netlist (as exported from Xschem) directly into floor planning?
v
m
Hello @Vijayan Krishnan, thank you! Yes, I looked at that and attempted to set the synth top level and black box. But got the error I posted about yesterday.
But from that issue, I think the conclusion was to keep Yosys in line and still have it perform synthesis?
v
https://github.com/The-OpenROAD-Project/OpenLane/issues file github issue by filling issue template carefully and wait for solution
If you've good understand of tcl script update locally https://github.com/The-OpenROAD-Project/OpenLane/blob/master/scripts/openroad/floorplan.tcl and use your netlist directly and run the flow
m
@Vijayan Krishnan thank you for your help! I will do so.
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