@JC first of all the schematic netlist (generated with xschem) is not wrapped into

.subckt / .ends

(these are commented). To have these uncommented regenerate the spice netlist with option

Simulation-> LVS netlist: top level is a .subckt

I also see the schematic pin order does not match the order of the netlist extracted from the layout. In xschem you can define the pin ordering in various ways: In your inverter schematic select the '`A`' pin, press

Shift-s

and set the object number to

0

. This will ensure this pin will be the first (position=0). Then select pin '`INV`' , press

Shift-s

and set the number to

1

, then select

VP

, set number to

2

and select

VN

setting its number to

3

. This will align pin ordering to the layout extracted netlist.