Hi Guys, I have the node "net3" in layout. If i run "goto net3", that node comes to highligth, but in the .spice generated to LVS on netgen, this node doesn't exist and the LVS fails. I really don't know what's happening. I tried to look for short nets to "net3" and i can't find. Some suggestion?

First, what command are you using for LVS? netgen's setup file has

# NOTE:  In accordance with the LVS manager GUI, the schematic is
# always circuit2, so some items like property "par1" only need to
# be specified for circuit2.

So if the layout is on the left, looks like your net3 equivalent node is shorted to gnd. The tap right above the

net3

text appears to be part of

net3

. Although you may have pwell drawn, this is not used in connectivity calculations, so you may be shorting through substrate. If you need pwell that is not connected to substrate, use dnwell surrounded by nwell.

Right, your nmos substrates are shorting. pwel layer has no effect on extraction.

Hm, do you suggest paint nwell(dnwell(pwell)))?

pwell is ignored. dnwell surrounded by a ring of nwell. Anything not nwell becomes pwell.