Hi, where are the gpio pins in this empty user wrapper? How to identify a particular analog pin in this wrapper? any help

1. I dont think this is the empty wrapper, seems filled to me. 2. Use verilog netlist. It explains function of each pin.

You can see a couple light blue pins on the left, just to the right of the light blue vertical power straps.

@Mitch Bailey those pins seems to have no connection with anything in the layout? Why is it so? Is this the correct wrapper where the instance of user layout has to be added?

You're looking at the empty wrapper which is only used to verify that the outer routing layers haven't been changed. Running

user_project_wrapper

through openlane should produce a design with the same outer power routing. I don't believe that the empty wrapper is used as a template, but rather as a check.

Does manually connecting the pins of user project analog empty wrapper to the instance of the layout of the analog design work?

I assume that if you manually wanted to do place and route, you could copy

user_analog_project_wrapper_empty.gds

to

user_analog_project_wrapper.gds

, read that into magic or klayout and make the changes there, but I have not tried it.

Could you tell what is the alternative to manually doing the place and route in case of analog designs?

One way would be to create an analog macro (eg.

user_proj_example

), and then make a verilog wrapper

verilog/rtl/user_analog_project_wrapper.v

that connects to

user_proj_example

and use openlane create the layout.

Is it possible to describe analog design using verilog?

Put all your analog circuits in a blackbox and then connect that box with verilog. See

verilog/rtl/user_analog_proj_example.v

and

verilog/rtl/user_analog_project_wrapper.v

in

caravel_user_project_analog

. You may want to modify the path widths for certain signals after routing.